M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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Has files: YesSubject: search.filters.subject.Electric current converters

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    Design issues in direct conversion receiver
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Gupta, Amit Kumar; Gupta, Sanjeev
    The wireless system is being rapidly proliferated in our life. The growing of capacity in wireless communication requires a new type of wireless communication method which does not affect current work on circuits and systems that can operate on gigahertz wide signals will undoubtedly be the wave of the future as pressures to supply multimedia services over wireless continue to build. To achieve the goal of single receiver which can act on various different standards the Direct Conversion Receiver (DCR) is the most suitable architecture. The DCR has been known for quite long years. There are number of design issues related to the implementation of DCR. This thesis presents the issues which are related to design of Direct Conversion along with the design issues related to LNA design.
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    ItemOpen Access
    Design of a high speed I/O buffer
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Rathore, Akhil; Parikh, Chetan D.
    In high speed serial transmission of data, output buffer creates the bottleneck. Current Mode Logic (CML) buffers have gained wide acceptance in most high speed serial interfaces as they reach speed of the order of Gbp/s. CML buffers achieves high speed due to low output voltage swing which reduces transition time. Presently CML buffers are designed with differential architecture and uses different bandwidth extension technique (inductive peaking, negative miller capacitance, active feedback) to increase the speed. At high frequency, input output coupling limits the bandwidth due to miller effect because of gate to drain capacitance. The proposed design incorporates the architecture which reduces miller effect, hence achieves high bandwidth. In this topology a source follower drives a common-gate stage which is an example of ‘unilateral’ amplifier, that is, one in which signal can flow only in one way over large bandwidths. It reduces unintended and undesired feedback. This CML buffer is designed for OC-192/STM-64 application to be used in limiting amplifier which is a critical block in optical system. OC-192/STM-64 works around 10Gbps.