M Tech Dissertations

Permanent URI for this collectionhttp://ir.daiict.ac.in/handle/123456789/3

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Now showing 1 - 8 of 8
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    Design and analysis of ultra wideband low noise amplifier
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2018) Dhami, Aarushi; Gupta, Sanjeev
    With the advent of wireless technology, ultra wide band systems due to their fast data rate transmission have gained momentum. One of the basic building blocks of the receiver - Low Noise Amplifier (LNA) has seen various design transformations. Initially, low noise amplifiers were designed for narrowband applications. However, their operation was limited. With more applications of wireless technology increasing day by day, there is a need to develop systems that can handle wide frequency ranges. Designing low noise amplifier for wideband application is a challenging task. The main objective is to achieve as low noise figure as possible and maintain a constant gain over the frequencies of interest. First and foremost task is to decide on the transistor technology to be employed. With the various technologies available, MOSFET is chosen for this work due to its various benefits and simplicity in the structure. In this work, a LNA has been first designed for a single frequency, 2.4 GHz. The work is then extended for 3-5 GHz range. A 2 stage amplifier is implemented with a reactive input matching network. The first stage is a cascode stage with the source of first MOSFET degenerated using an inductor. This is followed by a single CS stage which is also responsible for wideband output matching. The work then proceeds to the designing of amplifier for 3-10 GHz range. The implemented design is a 3 stage amplifier. The topology uses the concept of mutual inductance between the inductors. All the circuits are designed and simulated in Advanced Design System (ADS). Also, the technology used here is 0.18mm CMOS.
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    Low noise amplifier design at 2 GHz
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Mavani, Kausha; Gupta, Sanjeev
    Low Noise Amplifier (LNA) is one of the most important building blocks of any wireless receiver. In this an attempt has been made to study two types of LNA designs. The first design is the conventional which consists of the transistor, its biasing network and the input and output matching networks. The second design is an inductorless design which can be further customized to work over a large frequency range. The operating frequency studied in this thesis is 2GHz. A comparison has been made between the two designs and the values of gain and noise figure are satisfactory in both the designs.
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    Design of a CMOS variable gain amplifier
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Verma, Vivek; Parikh, Chetan D.
    In advanced CMOS technologies as device dimensions are decreasing, requirement for lower supply voltages are increasing to make certain device reliability. So, challenges for analog circuit designers are to discover new techniques to design analog circuits that can operate at lower supply voltages with desired performances. Another challenge for designer is to design a circuit with less power consumption while maintaining desired performance. In this thesis, a CMOS variable gain amplifier is designed to target above challenges. A fully differential, CMOS variable gain amplifier (VGA) has been designed for a 1.2- volt, low-power, 57-dB dynamic range, and high bandwidth. The VGA comprises of a control circuit, variable gain stages with common-mode feedback circuit. The gain of the VGA varies dB-linearly from -32 to 25 dB with respect to the control voltage, VC. Proposed VGA uses common-mode feedback (CMFB) circuit to fix and stabilize the output DC levels at a particular voltage depending on the input common-mode range (ICMR) requirement and output swing of the VGA. The proposed VGA uses capacitive neutralization technique to achieve high bandwidth operation. This VGA draws 1.25 mA current from a 1.2 V supply. The 3-dB bandwidth varies from 110 MHZ (at 25 dB gain) to 3828 MHz (at -32 dB gain). The proposed VGA is simulated for 0.18μm CMOS technology in LT-Spice with BSIM3V3 model.
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    Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Sesha Sai, Aduru Venkata Raghava; Parikh, Chetan D.
    In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor using a low-voltage gyrator topology with a feedback resistance, where feedback resistance is realized by a NMOS operating in triode region whose bias voltage tunes the inductance of the active inductor and hence the frequency of VCO. The simulation results shows that this VCO operates in a 1.19 GHz to 2.49 GHz , while consuming 1.09 mW from a 1.2V power supply. The VCO’s phase noise level is -86.9 dBc/Hz at 1 MHz offset from a 1.55 GHz carrier. The deviation of the phase noise is 11.5 dBc/Hz during this tuning range. All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology.
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    Design of low voltage high performance voltage controlled oscillator
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Ramesh, R; Nagchoudhuri, Dipankar; Mandal, Sushanta Kumar
    In this thesis an ultra low voltage differential capacitive feedback VCO is being proposed .The VCO operates at very low supply voltage of 0.6V.The VCO uses techniques like Forward Body Bias (FBB), and capacitive feedback to achieve high performance in terms of phase noise and output voltage swing. It uses differential MOS varactors for frequency tuning due to which all low frequency noise such as flicker noise gets rejected. Inductor was designed and it was simulated in IE3D electromagnetic simulator to achieve good Quality factor. This VCO achieves a very low phase noise of -119dBc/Hz@1-MHz offset frequency, power consumption of 3.27mW, and tuning range of 6% .All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology
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    Linearity enhancement technique for low noise amplifiers
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Purohit, Amit Gopal M.; Gupta, Sanjeev
    The development of CMOS technology in to deep sub micron enables the use of such technology for implementation for GHz RF circuits. Personal communication needs a low cost and low noise RF transceiver for cellular applications using CMOS technology. Low Noise amplifier is one of the basic building blocks in any receiver system. The LNA determines the overall system’s noise performance, as it is first gain block after antenna. LNA must amplify the input signal with lowest noise possible because it decides the whole device’s performance under noisy signal. In order to have high receiver sensitivity the LNA is required to have not only low noise figure but also high gain and low input VSWR.

    Normally, LNA design involves the tradeoff between noise figure, gain, linearity and power consumption. Consequently, the goal of LNA design is to meet system requirements with minimum noise figure and highest possible linearity. This thesis attempts to propose a linearity enhancing technique to simultaneously match high linearity and low noise figure requirements. The design is based upon the third order intermodulation product (IM3) and output current equations of MOSFET when it is subjected to an ac input signal. By using these expressions, the design principle and advantages for the mentioned LNA technique are explained.

    In this thesis a linearity enhancement technique is proposed which increases third order intermodulation product of low noise amplifier (IIP3) up to +10 dBm without a large increase in overall noise figure. Input impedance of low noise amplifier is matched to 50Ω while output impedance is kept high and unmatched. Prelayout simulation results, layout and postlayout simulation results are given to show that the technique really works satisfactory and gives good linearity.

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    Extremely low voltage operational amplifier design with rail-to-rail input common mode range
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Malviya, Yogesh; Nagchoudhuri, Dipankar
    Increasing trends towards battery operated systems demand circuits to be designed at low voltages. Low voltage operation severely limits the operational amplifier as a voltage buffer as the input common mode range available is very limited. This work deals with designing a very low voltage amplifier that can be used as a unity gain buffer. The architecture is based on using an operational amplifier in conjunction with an adapter circuit. The compliance voltage of the tail current source is maintained constant by comparing with a reference voltage using negative feedback action. The amplifier has been designed in 0.18µm technology at a supply voltage of 0.8 Volts. The amplifier gives a constant performance for varying common mode voltage as is demanded for a rail-to-rail amplifier. Designed amplifier gives a gain of 77.4dB with an input stage transconductance ‘Gm’ variation of just 1.29 % over the entire input common mode range.
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    Novel architecture for a CMOS low noise amplifier at 2.4 GHz
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2005) Ray, Anuradha; Parikh, Chetan D.
    Radio frequency design has been one of the major research areas in the recent past. Emergence of several Wireless Communication standards has demanded availability of different analog blocks for use in transceivers with different constraints, imposed by the nature of application. Particularly, lot of research has been carried out in CMOS technology, due to its low cost nature. LNA is one of the most important building blocks in the front end of the wireless communication systems. It determines the noise performance of the overall system, as it is the first block after the antenna. With technology scaling, the transistor’s cut off frequency continues to increase, which is desirable for improving the noise performance of CMOS circuit. Some other advantages like low cost, high level of integration motivates research of RF modules using CMOS technology. In recent years valuable research is done on CMOS LNA design in submicron technologies: from topology investigation to various new ideas on improvement of low power consumption, low noise figure, high gain, smaller space and low supply voltage. In this thesis, a new LNA architecture is reported, that consumes less power compared to other existing architectures, while providing the same gain, noise figure, CP-1dB and IIP3 figures. The new architecture achieves this better performance by combining the beneficial properties of two existing architectures – Lee’s inductive input stage, and the current-reuse (or the CMOS inverter amplifier) architecture. Detailed design procedures, and Spice simulation results are presented in the thesis, along with a brief survey of noise sources in MOSFETs, and a literature survey of existing LNA architectures.