HDL implementation of a node of bayesian polytree interface

Abstract

In this thesis, we have particularly focussed on the aspects of the hardware implementation of the Bayesian inference framework within the George and Hawkins’ model. This framework is based on Judea Pearl’s belief propagation. Then we have presented a “hardware design space exploration" methodology for implementing and analysing the (digital and mixed-signal) hardware for the Bayesian (polytree) inference framework. This, particular, methodology involves: analyzing the computational/operational cost and the analysis of the proposed hardware architectures of this particular computational model. Then we have explained Judea Pearl’s Belief Propagation Algorithm (BPA) and it’s hierarchical structure for the basic understandability to this thesis. In this thesis, we have implemented and proposed hardware designs of a single node of the hierarchical structure. Then we have described a single node operation in detail through various ways. This node operation contains some mathematical operations and we have described all those operations through a Bayesian Memory(BM) module. Now comes to the Implementation part, it contains general issues which have been faced during the implementation, and hardware implementation schemes. We have proposed two hardware implementation schemes. Both schemes are then analysed and obtained the results which are discussed and compared with each other. The results suggest that the computational time requires completing the whole operation (from child nodes to parent node) through the conventional processor (in serial manner) is very large compared to the Application Specific Hardware (in parallel manner). We then customized the architectures in different manner through the concept of parallelism and by utilizing more hardware resources. The results suggest that the customized architectures are more efficient then the regular one but it requires more complex control mechanism and other hardware resources. Here we have a trade-off between computational time and hardware resources. At the end we have concluded this thesis by comparing the obtained results through the simulations and added some future work too because this framework can be used in multiple applications and the hierarchical structure of this model could be different as per the user requirements. So the architecture would be different in those conditions.