Low power SAR ADC with split capacitor DAC

Abstract

Analog to Digital convertor and Digital to Analog convertors plays a vital role in Mixed Signal Design. Nowadays, the demand for designing of Low power, Moderate Resolution ADCs are increasing for Bio-medical applications and wireless sensor network application. SAR ADC is preferred for these kind applications. Comparator an important block, is most power consumer block in the SAR ADC. Resolution of SAR ADC is limited by the ratio error and parasitic capacitance of DAC capacitor. Also, the resolution of SAR ADC increases, area of the DAC increases and so does the power consumption.

In this thesis work a 12-Bit, low power Differential SAR ADC with Split capacitor DAC is implemented in UMC0.18μm CMOS technology. Differential architecture is implemented as it has good noise immunity than the single ended architecture. In order to design lower SAR-ADC, Dynamic regenerative latch comparator is implemented and the pre-amplifiers used in the comparator, that are biased in sub-threshold region. Split capacitor DAC is used to reduce the capacitances, the area of the DAC. For high resolution SAR ADC, calibration of the capacitor is DAC necessary. In this thesis, digital domain calibration of split capacitor DAC and Analog domain calibration of BWC DAC is explained. Implemented architecture works at 1.8V power supply, 110KS/s and consume 30.7μW power. 12 Bit low power Differential SAR ADC with Split capacitor DAC is implemented in UMC0.18μm technology and simulation is done in Cadence Virtuoso 6.1 simulator.