Low power BIST architecture for fast multiplier embedded core

Abstract

A typical core is deeply embedded in the chip of a system so that direct access to its input/output is not possible. Built in self test (BIST) structures are excellent solutions for testing embedded cores. In this work, an 8 ×8 modified Booth multiplier has been implemented with low power test pattern generators (TPG). Complete design was implemented using 0.25-micron technology. The BIST TPG architectures compared were: 8-bit binary counter, 8-bit gray counter and combination of gray and binary counter. Different TPGs have been compared in terms of average power dissipation, fault coverage. Reduction in power dissipation has been achieved by properly assigning the TPG outputs to the multiplier inputs, significantly reducing the test set length and suitable TPG built of a 4-bit binary and 4-bit gray counter. Experimental results show that combination of gray and binary counter can achieve power reduction from 21 %to 45% without affecting the quality of test. BIST architecture for modified Booth multiplier is proposed. Proposed architecture covers stuck at faults, stuck open faults and non-feedback bridging faults. It also provides fault coverage greater than 98 % for stuck-at faults, stuck-open faults and non-feedback faults.