Efficient scan-based BIST scheme for low heat dissipation and reduced test application time

Abstract

Switching activity during test application can be significantly higher than that during normal circuit operation in many circuits. This is due to the fact that the correlation between consecutive test vectors is significantly lower than that between consecutive vectors applied to a circuit during its normal operation. Circuits are increasingly tested at higher clock rates, if possible, at the circuit’s normal clock rates (called at-speed testing). Consequently, the heat dissipation during test application is on the rise and is fast becoming a problem that requires close attention to avoid damaging CUTs. The use of scan DFT can further decrease the correlation between successive vectors applied to the next state inputs. This may lead to hazardous effects such as excessive heat dissipation, increased electro-migration rate and higher ground bounce noise that seriously affects the reliability of the circuit leading to unnecessary loss of yield. This work presents a simple yet efficient low hardware overhead testing scheme for scan-based built-in self-test (BIST) architecture that reduces switching activity in CUTs and test application time without compromising in the fault coverage. Firstly demonstrated is the existing Low Transition Random TPG (LT-RTPG) based test-per-scan scheme targeted for low heat dissipation during test by reducing the number of transitions at the cost of reduced fault coverage. A combined approach using both test-per-scan and test-per-clock application schemes is presented. This improves the fault coverage but at the cost of losing away, to a great extent, the advantage of lesser transitions that was gained using the low transition TPG. Given later is the proposed BIST capability built on top of a partial scan circuit adding above LT-RTPG as the TPG and MISR for signature analysis. This takes optimum advantage of the combined approach. Results show that the proposed BIST scheme gives satisfactory fault coverage (almost comparable to conventional LFSR) that too, with a large reduction in test lengths and transitions.