Implementation of RSA-Decryption module ob FPGA

Abstract

"This work proposes a performance improved Montgomery Multiplication (MM) architecture and an area improved Montgomery Multiplication architecture which can be used in Montgomery exponential operation. In this architectures, instead of simple Carry Propagation Adder (CPA), Carry Save Adder (CSA) is used to reduce carry propagation delay. To improve the performance, critical delay path is taken as multicycle path using designing a timer. To improve the area, a single CSA is reused for all the types of addition operation. Inputs and Outputs of these architecture are in binary format, but the intermediate results are in carry save format. RSA Encryption/Decryption modules are implemented on FPGA which is based on Montgomery Modular multiplication. To generate the test vectors for the functional verification of these architectures, an RSA Calculator framework is designed which generates public and private keys for RSA algorithm. Several CSA based Montgomery Architecture are implemented and compared with targeting FPGA (Spartan-3E, XC3S500E) and 45 nm technology library. Comparison results are showing that there is a significant improvement in performance with performance improved architecture and a significant improvement in area with cost of extra clock cycles for the area improved CSA based architecture.v"