HDL implementation and study of ANN architecture mapping onto multiple processing nodes

Abstract

A general methodology has implemented on several Processing Nodes (PN) to be connected to form an Artificial Neural Network (ANN). This design has multiple Activation functions on the same architecture which makes it different from the currently existing designs i.e. ANNA and CNAPS . Requirement of the buses, that have used, in the design is less, compared to CNAPS design. For the implementation of the activation functions, Piece wise linear (PWL) approximation algorithm has used for exponential and multiplication formulas, using Shifters and Adders. The inputs are fully connected to the neuron through a connection Memory that manage the connection scheme as per requirement. Fixed-point number system is used for storing the floating values on the hardware with fixed<8,6> type, which has 0.015625 precision or accuracy. Two platforms has compared by implementing an example on it and found that FPGA platform has some limitation compared to ASIC one. But for some application FPGA is also more advantageous than ASIC.