Design of prominent single precision 32-bit floating-point adder using single electron transistor operating at room temperature

Abstract

The floating-point (FP) arithmetic plays the most important role in computer systems. Many of the digital signal processing systems use floating-point algorithms for floating-point computation, arithmetic operation, and real-number manipulation, and each operating system is essentially responsible for special floating-point cases such as underflow and overflow. Here we are using Single-electron transistor (SET) for floating-point addition. SET offers new functionalities that have no CMOS counterpart. This further results in miniaturization with better performance. Arithmetic operations and approximation calculations of real numbers on modern-day computers are done using floating-Point unit using CMOS technology. In the earlier days, each computer manufacturer had used their own implementation for arithmetic operations in their computer. For a long period, arithmetic operations between different computers varied on bases, significant and exponent sizes, formats, etc. And every company kept implementing their own model until the IEEE 754 standard defined a universal format. This research aims to implement a 32-bit binary floating-point adder using SET according to this IEEE 754 standard. Floating-point addition is the most difficult activity as it incurs more delay and power consumption. We compare the performance of SET based floating-point adder and the CMOS (16nm) based floating-point adder using the simulation results in terms of power and delay. SET is utilized here to make new developments which is difficult to accomplish by CMOS. By using SET based floating-point adder, addition becomes faster while using less power. For simulation, CADENCE virtuoso is used. According to our results, SET based FP addition uses 79.70% less power and gives 97.67% faster results than CMOS based FP addition.