CMOS latched comparator design for analog to digital converters

Abstract

Conventional comparators are at the two extremes as far as power delay product and isolation between input and output is concern. Either they achieved very good isolation at the cost of power in the preamplifier or save the static power dissipation in preamplifier in the latching mode which increases the feed through. In this thesis work we propose an optimized CMOS Latch Comparator. The simulation result based on .18um technology, shows the working of the comparator at 500 MHz, with moderate power delay product and isolation compared with the conventional architecture.