Adaptive caches: a smart way to reduce leakage power dissipation in cache memories

Abstract

The advancement of circuit minimization in CMOS echnology has not only led to extraordinary improvements in microprocessor performance but has also caused the density of energy dissipation in a chip to increase. This increase in energy dissipation calls for advanced cooling technologies and results in a bulky, less portable and unreliable system. In todays state-of-the-art microprocessors, cache memories account for a substantial portion of the total energy dissipation. Huge on-chip caches not only take up a lot of silicon area but also dissipate over 30% of the overall power. If an application uses a small part of cache, then the idle portion contributes to leakage power/energy. If, somehow, this idle portion could be switched off, there would be a great reduction in power dissipation of the complete circuit. This thesis aims to reduce the leakage power in the idle portion of cache by "reconfiguring" it according to the application’s demands without having an adverse affect on the performance of the processor. Smarter ways, which change the cache size and associativity dynamically, have been explored, implemented and analyzed.