Analysis of on-chip interconnects using prospective neural network techniques

Abstract

With the advancement in technology the number of transistors being fabricated on a single integrated chips (IC) increase manifold as stated in Moore’s law. Due to this increase in the transistors and thereby shrinking of the devices one of the major problematic areas for designers are interconnects which are responsible for the connection of the devices with each other and to power supply and ground. Thus analysis of on-chip interconnect is a necessary for designing a circuit. The mathematical representation of interconnect using finite difference time domain (FDTD) methodology with CMOS receiver is proposed in this research. The model used for the purpose is a driver-interconnect-load (DIL) model. In order to analyze and further design interconnect circuits, neural network techniques has been employed. Levenberg-Marquardt (LM) algorithm is used for implementing back-propagation in neural network (NN) design. NN based models have been extensively explored for classification, pattern recognition applications, image-speech processing, system and control identification, medical diagnosis, finance, etc. However, this has been very limitedly explored and adopted for optimization, designing and performance evaluation of VLSI circuits and systems. The optimization and designing of billions of transistors is a time consuming task. The NN based model efficiently automates the complete process. The dataset for training the network has been created using HSPICE . The accuracy of the proposed NN based model is assessed using regression, mean square error and error histogram. Further graphene materials such as multilayer graphene nanoribbon (MLGNR) has been explored as an alternative material for the DIL system. Its application is also validated in ring oscillator thereby proving a superiority over the traditional materials for interconnect system.