Parasitic Extraction and Performance Assessment using Experimental Analysis of rGO Interconnects for PCB Designs

Abstract

In this work, a novel reduced graphene oxide (rGO) interconnects for printed circuit boards (PCBs) designs are investigated using experimental analysis. rGO is a newly investigated and prominent material owing to its good electrical, thermal, mechanical and chemical properties. The prospective rGO is benchmarked with respect to conventional copper (Cu) based interconnects. Multiple interconnect device samples are fabricated physically by using FR4 copper clad for the analysis. These interconnect devices samples are used for the experimental analysis. The current-voltage (I-V) characteristics of these rGO and Cu interconnects are observed for linearity. The parasitic extraction of these interconnects is carried out using inductance-capacitance-resistance (LCR) meter. The characteristics of parasitic elements with respect to varying frequency range from 100 Hz to 10 MHz has been determined and analyzed in detail with the help of LCR meter. The frequency dependent behavior by extracting parasitic elements of the chip interconnects are observed for rGO interconnect and compared with the Cu interconnect device samples. The attenuation and slew rate performance parameters are determined with the help of digital storage oscilloscope (DSO). This work also consists of the comparison of the parasitic elements extracted and the parasitic elements obtained with analytical model. The experimental setups for all the systematic series of experiments are discussed in detail. The performance assessment analysis of the interconnects estimating the delay, power, attenuation and slew rate.