Theses and Dissertations

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Subject: search.filters.subject.Large scale integration

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    Study of power in CR-SRAM in context of precharge reference voltage.
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2013) Rupapara, Kripal D.; Zaveri, Mazad S
    In Morden times power dissipation in electronic circuits has become more important due to increase use of portable and handheld devices. Increased operating frequency results in more power consumption in almost every VLSI circuits. Scaling in integrated circuit technology directly paves way to increased package density, thereby increasing on chip power. With continuous scaling, low power design techniques results in efficient use of silicon die. Semiconductor memories are most important subsystems of modern digital systems. Modern IC’s allocate 70% of the total chip area to memory design. Large fraction of power is consumed by memory circuits, if we can reduce power consumed by memory structure can reduce overall power consumption. This thesis is mainly concentrated on various components of power consumption in digital circuits, operation of SRAM, various technique to reduce power in SRAM and finally illustrates charge recycling SRAM for lower power consumption.
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    Novel 7T SRAM cell design for low power cache applications
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Joshi, Srawan Kumar; NagChoudhuri, Dipankar
    Scaling in integrated circuit technology directly paves way to increased package density, thereby increasing onchip power. With continuous scaling, low power design techniques results in efficient use of silicon die. Semiconductor memories are most important subsystems of modern digital systems. Modern IC’s allocate 70% of the total chip area to memory design. SRAM is used as on chip cache memory. A major part of the power consumption in any memory architecture is due to charging and discharging of highly capacitive bitlines and wordlines. Existing techniques mainly concentrated on the reduction of power due to the capacitive bitlines and wordlines. In this thesis, a new 7T SRAM cell has been proposed with a single bitline architecture which reduces the dynamic power consumption to a great extent. This proposed design resulted in power reduction of write ‘0’ and read ‘0’ operation, based on the fact that the majority of the cache writes are 0’s. A memory array of size 256Kb (512x512) was designed using the basic 6T SRAM and propsed 7T SRAM cell to carry out the simulations and compare the results for power optimization. The simulations were done using Cadence Virtuoso (ADE) tool in gpdk180 library using 0.18μm technology. With the proposed SRAM cell implementing 256Kb memory array, reduction of write power (approximately 80%) and read power (approximately 55%) is achieved compared to conventional SRAM array. There is an area overhead of 28.76% using the present 180nm technology.
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    ItemOpen Access
    Design of low power and high speed decoder for 1MB memory
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Gupta, Punam Sen; Nagchoudhuri, Dipankar
    Technology scaling is accompanied by rise in leakage power dissipation. This thesis proposes a voltage controllable circuit in the feedback path of the decoder, which drastically reduces the standby leakage current with minimum loss in speed and slightly overheads in terms of chip area. This circuit generates slightly lower supply voltage when the load circuitry is in the standby mode thereby raises the Vt of the CMOS transistors and hence reduces leakage power dissipation The overall power dissipation of a 7x128 decoder is reduced from 0.928mW to 0.584mW for 1Mb Memory with voltage controllable circuit, namely 37% lowering in power dissipation. The operating voltage for the design is 1.2 V. Layout is done in magic 7.1 version in 180nm technology. The simulations are done in LT spice.