Implementation of digital multipliers based on single electron transistor

Abstract

As a solution to efficient implementation for faster, low power and extremelycompact Digital Multipliers, the Single Electron Transistor (SET) based Digitalmultiplier is proposed here. The SET has several advantages overCMOStechnologysuch as it is highly scalable and has ultra low power consumption. As the semiconductorindustry is facing the difficulties to extend ICs to recent applications and scaling ofCMOS, SET is a promising technology to be used as a building blocks. In the fieldof communication as specially in digital filters and in signal processing, multiplierplays an important role. Baugh Wooley and Booth multipliers employ parallelarchitecture hence they uses less number of adders and as a result consumes lesserarea. In the research work we have designed 8*8 bit Baugh Wooley multiplier,Booth multiplier and Array multiplier and their simulation results are validatedusing the CadenceVirtuoso ADE tool. The designed multipliers are implementedusing both 16 nm CMOS technology node and SET and as a conclusion comparisonbetween two is provided.From the simulation result, it is observed that multipliers based on SET outperformsits CMOS counterpart in all aspects. Considering above mentioned multipliers,SET based design is on an average 81% power efficient and 97% faster as comparedto 16nm CMOS based design.