Design and Implementation of AI Accelerator based Coprocessor for IoT node using RISC-V ISA

Abstract

Semiconductor industry has seen a considerable amount of growth in the processor industry. The design of a processor is focused on two aspects namely power and performance. Hardware acceleration is an efficient method to boost performance of any processor. This work shows how to accelerate multiply and accumulate (MAC) operation based algorithms on a general-purpose processor. A RISC-V based processor is designed with a tightly coupled coprocessor(TCC). Reduced Instruction Set Computer (RISC) architecture provides higher operating frequency and low power design as compared to Complex Instruction Set Computer (CISC) philosophy. The objective of this work is to realize a time-efficient architecture to accelerate the matrix multiplication for various applications. For this purpose, Single Instruction Multiple Data (SIMD) based coprocessor has been introduced in the proposed design which increases the capability of a resource constrained micro-controller. To achieve low power design, power techniques like clock gating, power gating are implemented. The SoC is designed using Verilog-HDL language. The processor has been synthesized with different 45nm and 180nm technology nodes for Application Specific Integrated Circuit (ASIC).